RTL Verification Engineer

Join us at Qblox as we revolutionize the landscape of quantum computing!  

We are seeking FPGA/RTL Verification Engineers to help us build a cutting-edge control stack for industrial scale quantum computers.

The stack Qblox develops is a distributed architecture that allows parallel qubit readout, control, intercommunication and other functions, ultimately interacting with the physical qubits using high frequency analogue signals. 

Imagine what it takes to talk to 1000 qubits, with nanosecond-level synchronization and all-to-all connectivity and that will give you an idea of design and verification challenges that we face.

We foster a culture of collaboration where every voice is heard and valued. You will have the opportunity to take ownership of your projects, influence technical decisions at higher levels and gain a broad understanding of what goes into our products. You will likely be working in cross-functional teams including electrical engineers, digital design engineers, application engineers and scientists and also have a chance to learn about the Quantum field from our in-house experts.

Your role:

• Analyze and evaluate requirements, supporting the design team in defining and verifying technical solutions.

• Work with technical documentation, including internal design specifications and vendor documentation for FPGAs, third-party ASICs, and software.

• Understand and interpret VHDL code, ensuring effective verification while collaborating with FPGA designers.

• Develop robust, self-checking testbenches at the module level and contribute to the enhancement of top-level testbenches when needed.

• Influence architecture and processes by proposing improvements based on best practices and industry trends.

• Collaborate closely with FPGA and embedded software engineers, acting as a technical sparring partner to ensure high-quality verification.

• Drive continuous improvement by proactively suggesting new methodologies, tools, and advancements in the FPGA/ASIC verification domain.

Enough about us, what about you?

To truly thrive in this role, we envision that you bring the following:

• A driven RTL verification engineer that has been working in a similar role and R&D environment for 5+ years.

• Results-driven mindset with a strong sense of ownership and accountability.

• Good communication skills and a collaborative approach to problem-solving.

• Expertise in verification planning, defining verification strategies, and implementing self-checking testbenches.

• Verification frameworks (preferably UVM, especially PyUVM).

• Experience with Python in object-oriented programming fashion.

• Experience with scripting languages (Python, Shell, TCL/Tk) for automation and workflow optimization.

• Strong understanding of VHDL to read, understand, and verify designs.

• High-end simulator tools (e.g. Cadence Xcelium, Synopsys VCS).

• Familiarity with processor and bus-system architecture (e.g. AMBA AXI, Avalon, etc).

• Version control proficiency using Git.

Optional nice-to-haves:

• Knowledge and experience of Cocotb is a huge plus.

• Open-Source simulator tools (e.g. NVC, GHDL).

• C/C++

• SystemVerilog

• Working with CI/CD (especially with GitLab)

• Knowledge about container technologies (Podman/Docker)

• Hands-on experience with FPGA (Xilinx or Intel) or ASIC toolchains

• Experience in the Quantum field